Reset Interfaces - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Table 27-7: User Clock Parameters
Parameter Name
Enable HPS-to-FPGA user 0
clock
User 0 clock frequency
Enable HPS-to-FPGA user 1
clock
User 1 clock frequency
Enable HPS-to-FPGA user 2
clock
User 2 clock frequency
Related Information
Selecting PLL Output Frequency and Phase
Clock Frequency Usage
The clock frequencies you provide are reported in a Synopsys Design Constraints File (.sdc) generated by
Qsys. The .sdc file will be referenced in the system .qip file when the system is generated.
Related Information
Selecting PLL Output Frequency and Phase
•
• Clock Manager
For general information about clock signals, refer to the Clock Manager chapter in the Cyclone V Device
Handbook, Volume 3 .

Reset Interfaces

You can enable the resets on an individual basis through the FPGA Interfaces tab under the Resets
section.
Table 27-8: Reset Parameters
Parameter Name
Enable HPS-to-FPGA cold reset
output
Instantiating the HPS Component
Send Feedback
Parameter Description
Enable main PLL from HPS-to-
FPGA
Specify the maximum expected
frequency for the main PLL
Enable peripheral PLL from HPS-
to-FPGA
Specify the maximum expected
frequency for the peripheral PLL
Enable SDRAM PLL from HPS-to-
FPGA
Specify the maximum expected
frequency for the SDRAM PLL
on page 2-1
Parameter Description
Enable interface for HPS-to-FPGA
cold reset output
h2f_user0_clock
h2f_user1_clock
h2f_user2_clock
on page 27-15
on page 27-15
h2f_cold_reset
Clock Frequency Usage
Clock Interface Name
Interface Name
Altera Corporation
27-9