Message Object Reconfiguration For Frame Transmission - Altera cyclone V Technical Reference

Hard processor system
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Message Object Reconfiguration for Frame Transmission

The following fields of a message object can be changed without clearing
Data0[7:0] to Data7[7:0]
TxRqst
NewDat
MsgLst
IntPnd
Message Object Reconfiguration for Frame Transmission
To configure a message object to transmit data frames, set the
set
to 1.
RmtEn
Before changing any of the following configuration and control bits, you must set
Dir
RxIE
TxIE
RmtEn
EoB
UMask
Msk[28:0]
MXtd
MDir
The following fields of a message object can be changed without clearing
ID[28:0]
Xtd
DLC[3:0]
Data0[7:0] to Data7[7:0]
TxRqst
NewDat
MsgLst
IntPnd
CAN Controller Address Map and Register Definitions
The address map and register definitions for the HPS-FPGA bridge consist of the following regions:
• CAN Controller Module 0
• CAN Controller Module 1
Related Information
Introduction to the Hard Processor System
The base addresses of all modules are also listed in the Introduction to the Hard Processor System
chapter.
http://www.altera.com/literature/hb/cyclone-v/hps.html
Altera Corporation
MsgVal
field to 1, and either set
Dir
MsgVal
on page 1-1
cv_5v4
2016.10.28
:
to 0 or
UMask
to 0:
MsgVal
:
CAN Controller
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