L4 Slave Interface - Altera cyclone V Technical Reference

25-10

L4 Slave Interface

Figure 25-4: CAN Core in Combined Mode
L4 Slave Interface
The host processor accesses data, control, and status information of the CAN controller through the L4
slave interface. The slave interface supports 32-bit accesses only.
Note: This interface does not support error responses.
Clocks
The CAN controller operates on the
the L4 slave interface and the
The
can_clk
example, for a CAN bus interface operating at a 1 Mbps baud rate, the
least 8 MHz. The
frequency.
can_clk
Related Information
Clock Manager
For more information about the
Software Reset
Software initialization is done by setting the
group (
protogrp
bus off condition occurs on the CAN link. The bit is also set through the hardware reset input described in
Hardware Reset.
Due to the synchronization mechanism between the two clock domains, there might be a delay until the
value written to the
read the
Init
The bus off recovery sequence cannot be shortened by setting or resetting the
tion about bus off, refer to the CAN Protocol Specification 2.0 parts A and B, available from the Bosch
website.
Related Information
Hardware Reset
•
Bosch Semiconductor
•
Altera Corporation
CAN_RXD
CAN_TXD
l4_sp_clk
can_clk
clock must be programmed to be at least eight times the CAN bus interface speed. For
clock can operate at a clock frequency that is equal to or greater than the
l4_sp_clk
on page 2-1
l4_sp_clk
) in the CAN controller register map. This bit is set through the CAN protocol when a
bit can be read back. To assure that the previous value written has been accepted,
Init
bit before setting it to a new value.
on page 25-11
CAN Controller
RX
Vcc TX
CAN Core
and clock inputs. The
can_clk
is used to operate the CAN core.
and clocks, refer to the Clock Manager chapter.
can_clk
bit in the CAN control register (
Init
clock is used by
l4_sp_clk
clock must be set to at
can_clk
) in the protocol
CCTRL
bit. For more informa‐
Init
CAN Controller
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cv_5v4
2016.10.28