Can Controller Programming Model - Altera cyclone V Technical Reference

25-12

CAN Controller Programming Model

Table 25-3: Message Object Interrupt Registers
Register
MOIPA
MOIPB
MOIPC
MOIPD
The
MOIPX
CAN Controller Programming Model
Software Initialization
The software initialization is started by setting the
the bit is 1, messages are not transferred to or from the CAN bus, and the
Init
is held in the high state. Setting the
To initialize the CAN controller, the host processor must program the CAN bit timing (
message objects that will be used for CAN communication. If a message object is not needed, it is
sufficient to set the
ization. You must set up the entire message object before setting
objects are set up through either message interface register set.
Access to the CAN bit timing (
and bits in the CAN control register (
Init
Setting the
transfer on the CAN bus by waiting for the bus to reach an idle state before it can take part in bus activities
and message transfers.
The initialization of the message objects is independent of the CAN controller initialization and can be
done anytime, but the message objects should all be configured to particular identifiers or set to not valid
before message transferring begins.
On power up, the message RAM has to be initialized. To initialize RAM, set the
bit in the CAN function register (
RAMInit
returns to 0 when RAM initialization completes. During RAM initialization, all message objects are
cleared to zero and the RAM ECC bits are initialized. Access to RAM is not allowed prior to or during
RAM initialization.
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Interrupt pending A register
Interrupt pending B register
Interrupt pending C register
Interrupt pending D register
register allows software to quickly detect which message object group has a pending interrupt.
bit of the message object to not valid (0), which is the default after RAM initial‐
MsgVal
) register is only enabled when the configuration change enable (
CBT
bit to 0 finishes the software initialization. The CAN core synchronizes itself to the data
Init
Title
bit in the CAN control register (
Init
bit does not change any configuration registers.
Init
) are both set to 1.
CCTRL
) in the protocol group (
CFR
Message Objects
1 to 32
33 to 64
65 to 96
97 to 128
CCTRL
CAN bus output
CAN_TXD
CBT
bit to valid (1). The message
MsgVal
bit to 1, then set the
Init
) to 1. The
protogrp
cv_5v4
2016.10.28
) to 1. While
) register and
)
CCE
bit
RAMInit
CAN Controller
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