Configuring The External Memory Interface - Altera cyclone V Technical Reference

27-14

Configuring the External Memory Interface

The following steps show you how to enable the peripheral signals:
1. Select FPGA in the peripheral pin multiplexing selection drop-down box.
2. Export the peripheral signals out of Qsys system.
3. In the software, connect the signals to the FPGA I/O pins.
Note: When routed to the FPGA, some HPS peripherals require additional pipeline support in the
connected soft logic. Routing into the FPGA circumvents the pipelining available in the HPS I/O.
Refer to the relevant HPS peripheral chapter for details.
Configuring the External Memory Interface
The SDRAM tab is one of four tabs on the HPS component. This tab contains the PLL output frequency
and phase group.
The HPS supports one memory interface implementing double data rate 2 (DDR2), double data rate 3
(DDR3), and low-power double data rate 2 (LPDDR2) protocols. The interface can be up to 40 bits wide
with optional error correction code (ECC).
Configuring the HPS SDRAM controller is similar to configuring any other Altera SDRAM controller.
There are several important differences:
• The HPS parameter editor supports all SDRAM protocols with one tab. When you parameterize the
SDRAM controller, you must specify the memory protocol: DDR2, DDR3, or LPDDR2.
To select the memory protocol, select DDR2, DDR3, or LPDDR2 from the SDRAM Protocol list in the
SDRAM tab. After you select the protocol, settings not applicable to that protocol are disabled.
• Many HPS SDRAM controller settings are the same as for Altera's dedicated DDR2, DDR3, and
LPDDR2 controllers. This section only describes SDRAM parameters that are specific to the HPS
component.
• Because the HPS memory controller is not configurable through the Quartus Prime software, the
Controller and Diagnostic tabs are not present in the HPS parameter editor.
• Some settings, such as the controller settings, are not included because they can only be configured
through the register interface, for example by software running on the MPU.
• Unlike the memory interface clocks in the FPGA, the memory interface clocks for the HPS are initial‐
ized by the boot-up code using values provided by the configuration process. You can accept the values
provided by UniPHY, or you can use your own PLL settings, as described in Selecting PLL Output
Frequency and Phase.
Note: The HPS does not support external memory interface (EMIF) synthesis generation, compilation, or
timing analysis.
The HPS memory controller cannot be bonded with a memory controller on the FPGA portion of the
device.
For detailed information about SDRAM controller parameters, refer to the following chapters:
Related Information
• Selecting PLL Output Frequency and Phase
http://www.altera.com/literature/hb/external-memory/emi_parameters.pdf
•
The Implementing and Parameterizing Memory IP chapter in the External Memory Interface Handbook.
Altera Corporation
on page 27-15
2016.10.28
Instantiating the HPS Component
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