Pll Reference Clocks - Altera cyclone V Technical Reference

27-10

PLL Reference Clocks

Parameter Name
Enable HPS warm reset
handshake signals
Enable FPGA-to-HPS debug
reset request
Enable FPGA-to-HPS warm
reset request
Enable FPGA-to-HPS cold reset
request
Related Information
Reset Manager
For more information about the reset interfaces, refer to Functional Description of the Reset Manager in the
Reset Manager chapter in the Cyclone V Device Handbook, Volume 3 .
PLL Reference Clocks
Table 27-9: PLL Reference Clock Parameters
Parameter Name
Enable FPGA-to-HPS peripheral
PLL reference clock
Enable FPGA-to-HPS SDRAM
PLL reference clock
Related Information
Clock Manager
For general information about clock signals, refer to the Clock Manager chapter in the Cyclone V Device
Handbook, Volume 3 .
Altera Corporation
Parameter Description
Enable an additional pair of reset
handshake signals allowing soft
logic to notify the HPS when it is
safe to initiate a warm reset in the
FPGA fabric.
Enable interface for FPGA-to-HPS
debug reset request
Enable interface for FPGA-to-HPS
warm reset request
Enable interface for FPGA-to-HPS
cold reset request
on page 3-1
Parameter Description
Enable the interface for FPGA fabric
to supply reference clock to HPS
peripheral PLL
Enable the interface for FPGA fabric
to supply reference clock to HPS
SDRAM PLL
on page 2-1
Interface Name
h2f_warm_reset_handshake
f2h_debug_reset_req
f2h_warm_reset_req
f2h_cold_reset_req
Clock Interface Name
f2h_periph_ref_clock
f2h_sdram_ref_clock
Instantiating the HPS Component
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cv_5v4
2016.10.28