Mpu Subsystem - Altera cyclone V Technical Reference

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MPU Subsystem

MPU Subsystem
The MPU subsystem features the dual ARM Cortex-A9 MPCore processors.
Related Information
Cortex-A9 Microprocessor Unit Subsystem
ARM CoreSight Debug Components
The following lists the ARM CoreSight debug components:
• Debug Access Port (DAP)
• System Trace Macrocell (STM)
• Trace Funnel
• Embedded Trace FIFO (ETF)
• AMBA Trace Bus Replicator (Replicator)
• Embedded Trace Router (ETR)
• Trace Port Interface Unit (TPIU)
• Embedded Cross Trigger (ECT)
• Program Trace Macrocell (PTM)
Related Information
CoreSight Debug and Trace
Interconnect
The interconnect consists of the L3 interconnect, SDRAM L3 interconnect, and level 4 (L4) buses. The L3
interconnect is a partially-connected switch fabric.
Related Information
System Interconnect
HPS-to-FPGA Interfaces
The HPS-to-FPGA interfaces provide a variety of communication channels between the HPS and the
FPGA fabric. The HPS is highly integrated with the FPGA fabric, resulting in thousands of connecting
signals. Some of the HPS-to-FPGA interfaces include:
• FPGA-to-HPS port
• HPS-to-FPGA port
• Lightweight HPS-to-FPGA port
• FPGA-to-SDRAM interface
Related Information
HPS-FPGA Bridges
Altera Corporation
on page 10-1
on page 7-1
on page 8-1
on page 9-1
Introduction to the HPS Component
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cv_5v4
2016.10.28