Using Unassigned Io As Loanio - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Using Unassigned IO as LoanIO

You can utilize unused HPS IOs as LoanIO, which is directly driven by the FPGA and can be used as
input, output, or bi-directional IO.
Each LoanIO port has an input, output, and output enable, which directly controls the HPS IO functions.
The LoanIO only operates when the HPS registers have been set up in the pre-loader to allow their
operation. The LoanIO are asynchronous, thus no clocking is required.
The status of the LoanIO in the duration after HPS I/O is configured and before the FPGA is configured is
as follows: When the FPGA powers up and is "not" configured, inputs into the HPS from the FPGA are
driven to a logical 1. When the FPGA is configured the signal may toggle, and then will take on whatever
level the FPGA user design drives out.
Use the following steps to enable the LoanIO signals:
1. Select the Peripheral Pins Multiplexing tab in the HPS Megawizard.
2. Choose the corresponding LoanIO pins from the Peripherals Mux Table, and click the push button to
select/unselect it.
3. Export the peripheral signals out of the Qsys system.
4. In the Quartus Prime software, connect the user logic to the LoanIO interface to drive the HPS IOs.
Table 27-11: Generated Conduit Signal Interface
Conduit Name
._hps_io_gpio_inst_LOANIOXX
._h2f_loan_io_in
._h2f_loan_io_out
._h2f_loan_io_oe
Qsys will generate a full signal array for
must assign user logic to the specific signal array. For example, you have triggered LoanIO 40, so its
respective signal array is
Resolving Pin Multiplexing Conflicts
Use the Peripherals MUX Table to view pins with invalid multiple assignments.
Pins that have multiple peripherals assigned to them are highlighted in red color with the conflicting
peripherals in boldface font style. Solve the multiplexing conflicts by de-selecting peripherals that are
assigned to the pins, leaving only one peripheral, which is needed.
Peripheral Signals Routed to FPGA
You can route the peripheral signals to the FPGA fabric and assign them to the FPGA I/O pins.
Instantiating the HPS Component
Send Feedback
Direction
Bi-direction
Out
In
In
h2f_loan_io_in, h2f_loan_io_out
h2f_loan_io_in[40], h2f_loan_io_out[40]
Using Unassigned IO as LoanIO
Declarations
User must declare as a top-level pin; pin
assignment is hardcoded following the
HPS IO location.
HPS IO data input signal, output to
FPGA user logic.
HPS IO data output signal, input from
FPGA user logic.
HPS IO data output enable signal, input
from FPGA user logic.
, and
h2f_loan_io_oe
, and
h2f_loan_io_oe[40]
27-13
. You
.
Altera Corporation