Hardware Reset - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Hardware Reset

Each CAN controller has a separate reset signal. The reset manager drives the signals on a cold or warm
reset. The reset signal is synchronized to both clock domains and applied to the appropriate logic within
the CAN controllers.
Related Information
Reset Manager
For more information, refer to the Reset Manager chapter.
Taking the CAN Controller Out of Reset
When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset
until software releases it.
After the Cortex-A9 MPCore CPU boots, it can deassert the reset signal by clearing the appropriate bits in
the reset manager's corresponding reset register. For details about reset registers, refer to "Module Reset
Signals".
Interrupts
Each CAN controller generates two interrupt signals. One signal indicates error and status interrupts and
the other signal indicates message object interrupts. Both interrupt signals connect to the global interrupt
controller (GIC). Interrupts are enabled in the CAN control register (
(
protogrp
priority interrupt that is pending.
Error Interrupts
The following error conditions generate interrupts:
• Bus off—when the transmit error count is equal to or greater than 256, the bus off (
CAN status register (
• Error warning—when either the transmit error counter or the receive error counters reaches 96, the
error warning status (
set to 1.
Status Interrupts
The following status conditions generate interrupts:
• Receive OK—when the CAN controller receives a message successfully, the
register (
• Transmit OK—when the CAN controller transmits a message successfully, the
status register (
• Last error code—when a message is received or transmitted with an error, the
status register (
Message Object Interrupts
The
IntPnd
bit or
TxIE
interrupt pending registers. The interrupt pending registers are located in the message handler group
(
msghandgrp
CAN Controller
Send Feedback
on page 3-1
). The CAN interrupt register (
) in the protocol group (
CSTS
) bit in the CAN status register (
EWarn
) in the protocol group (
CSTS
) in the protocol group (
CSTS
) in the protocol group (
CSTS
bits from the message objects can generate interrupts when the corresponding message object
bit is set to 1. The table lists the location of message object interrupt information in the
RxIE
).
) in the protocol group (
CIR
) is set to 1.
protogrp
CSTS
) is set to 1.
protogrp
) is set to 1.
protogrp
) are set according to the error type.
protogrp
Hardware Reset
) in the protocol group
CCTRL
) indicates the highest
protogrp
) bit in the
BOff
) in the protocol group (
protogrp
bit in the CAN status
RxOK
bit in the CAN
TxOK
bits in the CAN
LEC
Altera Corporation
25-11
) is