Axi Bridge Fpga Interface Clocks - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Related Information
Clock Select
The boot ROM reads the clock select values to determine what frequency has been selected for the CPU
clock and any interface clock during boot.

AXI Bridge FPGA Interface Clocks

The AXI interface has an asynchronous clock crossing in the FPGA-to-HPS bridge. The FPGA-to-HPS and
HPS-to-FPGA interfaces are synchronized to clocks generated in the FPGA fabric. These interfaces can be
asynchronous to one another. The SDRAM controller's multiport front end (MPFE) transfers the data
between the FPGA and HPS clock domains.
•
f2h_axi_clock
•
h2f_axi_clock
•
h2f_lw_axi_clock
fabric
SDRAM Clocks
You can configure the HPS component with up to six FPGA-to-HPS SDRAM clocks.
Each command channel to the SDRAM controller has an individual clock source from the FPGA fabric.
The interface clock is always supplied by the FPGA fabric, with clock crossing occurring on the HPS side
of the boundary.
The FPGA-to-HPS SDRAM clocks are driven by soft logic in the FPGA fabric.
•
f2h_sdram0_clock
•
f2h_sdram1_clock
•
f2h_sdram2_clock
•
f2h_sdram3_clock
•
f2h_sdram4_clock
•
f2h_sdram5_clock
Peripheral FPGA Clocks
The HPS peripheral clocks are exposed when the peripheral signals are routed to the FPGA.
Table 28-4: Peripheral FPGA Clocks
emac_md_clk
emac_gtx_clk
emac_rx_clk_in
emac_tx_clk_in
HPS Component Interfaces
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on page 30-25
—AXI slave clock for FPGA-to-HPS bridge, generated in FPGA fabric
—AXI master clock for HPS-to-FPGA bridge, generated in FPGA fabric
—AXI master clock for lightweight HPS-to-FPGA bridge, generated in FPGA
—SDRAM clock for port 0
—SDRAM clock for port 1
—SDRAM clock for port 2
—SDRAM clock for port 3
—SDRAM clock for port 4
—SDRAM clock for port 5
Clock Name
AXI Bridge FPGA Interface Clocks
Description
Ethernet PHY management interface clock
Ethernet transmit clock that is used by the PHY in
GMII mode
Ethernet MAC reference clock from the PHY
Ethernet MAC uses this clock input for TX
reference
28-5
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