Memory-Mapped Interfaces - Altera cyclone V Technical Reference

2016.10.28
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This chapter describes the interfaces, including clocks and resets, implemented by the hard processor
system (HPS) component.
The majority of the resets can be enabled on an individual basis. The exception is the
which is always enabled.
You must declare the clock frequency of each HPS-to-FPGA clock for timing purposes. Each possible
clock, including ones that are available from peripherals, has its own parameter for describing the clock
frequency. Declaring the clock frequency for HPS-to-FPGA clocks specifies how you plan to configure the
PLLs and peripherals, to enable TimeQuest to accurately estimate system timing. It has no effect on PLL
settings.
Related Information
Avalon Interface Specifications
•
For Avalon protocol timing, refer to Avalon Interface Specifications .
HPS Component Interfaces
•
For information about instantiating the HPS component, refer to the Instantiating the HPS Component
chapter.
• Info Center
For Advanced Microcontroller Bus Architecture ( AMBA ) Advanced eXtensible Interface ( AXI )
protocol timing, refer to the AMBA AXI Protocol Specification v1.0, which you can download from the
ARM info center website.

Memory-Mapped Interfaces

FPGA-to-HPS Bridge
Table 28-1: FPGA-to-HPS Bridges and Clocks
Interface Name
f2h_axi_slave
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HPS Component Interfaces
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on page 28-1
Description
FPGA-to-HPS AXI slave interface
h2f_reset
Associated Clock Interface
f2h_axi_clock
28
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