Fpga-To-Hps Axi Slave Interface - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Parameter
Assert reset high
Cycles of initial reset
Related Information
• Memory-Mapped Interfaces
• Avalon Verification IP Suite User Guide

FPGA-to-HPS AXI Slave Interface

The FPGA-to-HPS AXI slave interface,
BFM for simulation with an instance name of
in the following table. The BFM clock input is connected to
Table 29-17: Configuration of FPGA-to-HPS AXI Slave BFM
AXI Address Width
AXI Read Data Width
AXI Write Data Width
AXI ID Width
You control and monitor the AXI slave BFM by using the BFM API.
Related Information
Memory-Mapped Interfaces
•
Mentor Verification IP Altera Edition User Guide
•
The Mentor Verification IP User guide provides details of the API and connection guidelines for the
AXI3 and AXI4 BFMs.
HPS-to-FPGA AXI Master Interface
The HPS-to-FPGA AXI master interface,
BFM for simulation with an instance name of
HPS-to-FPGA interface with the following address, data, and ID widths. The BFM clock input is
connected to
Simulating the HPS Component
Send Feedback
BFM Value
Off
0
on page 28-1
Parameter
on page 28-1
clock.
h2f_axi_clock
This parameter is off, specifying an active-low reset
signal from the BFM.
This parameter is 0, specifying that the BFM does
not assert the reset signal automatically.
, is connected to a Mentor Graphics AXI slave
f2h_axi_slave
f2h_axi_slave_inst
f2h_axi_clock
32
32, 64, or 128
32, 64, or 128
8
, is connected to a Mentor Graphics AXI master
h2f_axi_master
h2f_axi_master_inst
FPGA-to-HPS AXI Slave Interface
Meaning
. Qsys configures the BFM as shown
clock.
Value
. In Qsys, you can configure the
29-11
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