Fpga-To-Hps Sdram Interface - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Parameter Name
Enable FPGA Trace Port
Interface Unit
Enable boot from FPGA signals
Enable HLGPI Interface
Related Information
CoreSight Debug and Trace
•
Enabling the TPIU exposes trace signals to the device pins. Refer to the CoreSight Debug and Trace for
more information.
Booting and Configuration
•
For detailed information about the HPS boot sequence, refer to the Booting and Configuration.

FPGA-to-HPS SDRAM Interface

In the FPGA-to-HPS SDRAM Interface table, use + or – to add or remove FPGA-to-HPS SDRAM
interfaces.
You can add one or more SDRAM ports that make the HPS SDRAM subsystem accessible to the FPGA
fabric.
Instantiating the HPS Component
Send Feedback
Parameter Description
Enables an interface between the
trace port interface unit (TPIU) and
logic in the FPGA. The TPIU is a
bridge between on-chip trace
sources and a trace port. For more
information, refer to the CoreSight
Debug and Trace chapter.
Enables an input to the HPS
indicating whether a preloader is
available in the on-chip memory of
the FPGA. This option also enables a
separate input to the HPS indicating
a fallback preloader is available in
the FPGA memory. A fallback
preloader is used when there is no
valid preloader image found in flash
memory. For more information,
refer to Appendix A: Booting and
Configuration.
Enables a general purpose interface
that is connected to the General
Purpose I/O (GPIO) peripheral of
HPS. This is an input-only interface
with 14-bit width. This interface
shares the I/O pins with the HPS
DDR SDRAM controller.
on page 10-1
on page 30-1
FPGA-to-HPS SDRAM Interface
Interface Name
h2f_tpiu
h2f_tpiu_clock_in
h2f_tpiu_clock
f2h_boot_from_fpga
hps_io (hps_io_gpio_inst_
HLGPI[0..13])
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