Selecting Pll Output Frequency And Phase - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
http://www.altera.com/literature/hb/external-memory/emi_fd_hard_memory.pdf
•
The Functional Description--Hard Memory Interface chapter in the External Memory Interface
Handbook. "EMI-Related HPS Features in SoC Devices" describes features specific to the HPS SDRAM
controller.
• SDRAM Controller Subsystem

Selecting PLL Output Frequency and Phase

You select PLL output frequency and phase with controls in the PHY Settings tab. In the HPS, PLL
frequencies and phases are set by software at system startup. A PLL might not be able to produce the exact
frequency that you specify in Memory clock frequency. Normally, the Quartus Prime software sets
Achieved memory clock frequency to the closest achievable frequency, using an algorithm that tries to
balance frequency accuracy against clock jitter. This clock frequency is used for timing analysis by the
TimeQuest analyzer.
It is possible to use a different software algorithm for configuring the PLLs. You can force the Achieved
memory clock frequency box to take on the same value as Memory clock frequency, by turning on Use
specified frequency instead of calculated frequency in the PHY Settings tab, under Clocks.
Note: If you turn on Use specified frequency instead of calculated frequency, the Quartus Prime
software assumes that the value in the Achieved memory clock frequency box is correct. If it is not,
timing analysis results are incorrect.
Related Information
• http://www.altera.com/literature/hb/external-memory/emi_parameters.pdf
The Implementing and Parameterizing Memory IP chapter in the External Memory Interface Handbook.
• http://www.altera.com/literature/hb/external-memory/emi_fd_hard_memory.pdf
The Functional Description--Hard Memory Interface chapter in the External Memory Interface
Handbook. "EMI-Related HPS Features in SoC Devices" describes features specific to the HPS SDRAM
controller.
Using the Address Span Extender Component
The FPGA-to-HPS bridge and FPGA-to-HPS SDRAM memory-mapped interfaces expose their entire 4-
GB address spaces to the FPGA fabric. The address span extender component provides a memory-mapped
window into the address space that it masters. Using the address span extender, you can expose portions of
the HPS memory space without needing to expose the entire 4 GB address space.
You can use the address span extender between a soft logic master and an FPGA-to-HPS bridge or FPGA-
to-HPS SDRAM interface. This component reduces the number of address bits required for a master to
address a memory-mapped slave interface located in the HPS.
Instantiating the HPS Component
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Selecting PLL Output Frequency and Phase
on page 11-1
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