Lightweight Hps-To-Fpga Axi Master Interface - Altera cyclone V Technical Reference

29-12

Lightweight HPS-to-FPGA AXI Master Interface

Table 29-18: Configuration of HPS-to-FPGA AXI Master BFM
AXI Address Width
AXI Read and Write Data Width
AXI ID Width
You control and monitor the AXI master BFM by using the BFM API.
Related Information
Memory-Mapped Interfaces
•
Mentor Verification IP Altera Edition User Guide
•
The Mentor Verification IP User guide provides details of the API and connection guidelines for the
AXI3 and AXI4 BFMs.
Lightweight HPS-to-FPGA AXI Master Interface
The lightweight HPS-to-FPGA AXI master interface,
Graphics AXI master BFM for simulation with an instance name of
configures the BFM as shown in the following table. The BFM clock input is connected to
h2f_lw_axi_clock
Table 29-19: Configuration of Lightweight HPS-to-FPGA AXI Master BFM
AXI Address Width
AXI Read and Write Data Width
AXI ID Width
You control and monitor the AXI master BFM by using the BFM API.
Related Information
Memory-Mapped Interfaces
•
Mentor Verification IP Altera Edition User Guide
•
The Mentor Verification IP User guide provides details of the API and connection guidelines for the
AXI3 and AXI4 BFMs.
Altera Corporation
Parameter
on page 28-1
clock.
Parameter
on page 28-1
30
32, 64, or 128
12
h2f_lw_axi_master
h2f_lw_axi_master_inst
21
32
12
Value
, is connected to a Mentor
. Qsys
Value
Simulating the HPS Component
Send Feedback
cv_5v4
2016.10.28