Generating And Compiling The Hps Component - Altera cyclone V Technical Reference

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Generating and Compiling the HPS Component

Figure 27-2: Address Span Extender Components
Two address span extender components used in a system with the HPS.
Qsys System
Processor
You can also use the address span extender in the HPS-to-FPGA direction, for slave interfaces in the
FPGA. In this case, the HPS-to-FPGA bridge exposes a limited, variable address space in the FPGA, which
can be paged in using the address span extender.
For example, suppose that the HPS-to-FPGA bridge has a 1-GB span, and the HPS needs to access three
independent 1-GB memories in the FPGA portion of the device. To achieve this, the HPS programs the
address span extender to access one SDRAM (1-GB) in the FPGA at a time. This technique is commonly
called paging or windowing.
Related Information
Qsys System Design Components
•
For more information about the Altera Span Extender, refer to the Address Span Exdenter section in
the Qsys System Design Components chapter of the Qsys Design Handbook.
Qsys interconnect and System Design Components
•
For more information about the address span extender, refer to Bridges in the Qsys Interconnect and
System Design Components chapter in the Quartus
Generating and Compiling the HPS Component
The process of generating and compiling an HPS design is very similar to the process for any other Qsys
project. Perform the following steps:
1. Generate the design with Qsys. The generated files include an .sdc file containing clock timing
constraints. If simulation is enabled, simulation files are also generated.
2. Add <qsys_system_name>.qip to the Quartus Prime project. <qsys_system_name>.qip is the
Quartus Prime IP file for the HPS component, generated by Qsys.
3. Perform analysis and synthesis with the Quartus Prime software.
4. Assign constraints to the SDRAM component. When Qsys generates the HPS component (step 1), it
generates the pin assignment Tcl Script File (.tcl) to perform memory assignments. The script file name
Altera Corporation
DMA
M
512 MB
512 MB
Nios II
M
1 GB
M
Address Span
M
S
Extender
512 MB
Window
Address Span
S M
Extender
1GB
Window
Prime Handbook.
®
HPS
4 GB
S
FPGA-to-SDRAM
4 GB
Interface
S
FPGA-to-HPS
4 GB
Bridge
S
Instantiating the HPS Component
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2016.10.28