Reset Interface - Altera cyclone V Technical Reference

29-10

Reset Interface

Table 29-13: HPS Clock Output Interface Simulation Model
The Altera clock source BFM application programming interface (API) applies to all the BFMs listed in
this table. Your Verilog interfaces use the same API.
h2f_user0_clock
h2f_user1_clock
h2f_user2_clock
h2f_tpiu_clock
Related Information
Memory-Mapped Interfaces
Reset Interface
The HPS reset request and handshake interfaces are connected to Altera conduit BFMs for simulation.
Table 29-14: HPS Reset Input Interface Simulation Model
You can monitor the reset request interface state changes or set the interface by using the API listed.
Interface Name
f2h_cold_reset_req
f2h_debug_reset_req
f2h_warm_reset_req
h2f_warm_reset_handshake
Table 29-15: HPS Reset Output Interface Simulation Model
The Altera reset source BFM application programming interface applies to all the BFMs listed.
h2f_reset
h2f_cold_reset
h2f_debug_apb_reset
Table 29-16: Configuration of Reset Source BFM for HPS Reset Output Interface
The HPS reset output interface is connected to a reset source BFM. Qsys configures the BFM as shown in
the following table. The parameter value of the instantiated BFM is configured for HPS simulation.
Altera Corporation
Interface Name
on page 28-1
f2h_cold_reset_req_
inst
f2h_debug_reset_req_
inst
f2h_warm_reset_req_
inst
h2f_warm_reset_
handshake_inst
Interface Name
h2f_user0_clock_inst
h2f_user1_clock_inst
h2f_user2_clock_inst
h2f_tpiu_clock_inst
BFM Instance Name
h2f_reset_inst
h2f_cold_reset_inst
h2f_debug_apb_reset_inst
BFM Instance Name
API Function Names
get_f2h_cold_rst_req_n()
get_f2h_dbg_rst_req_n()
get_f2h_warm_rst_req_n()
set_h2f_pending_rst_req_n()
get_f2h_pending_rst_ack_n()
BFM Instance Name
Simulating the HPS Component
cv_5v4
2016.10.28
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