Clock And Reset Interfaces - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
BFM API Hierarchy Format
For post-fit simulation, you must call the BFM API in your test program with a specific hierarchy. The
hierarchy format is:
<DUT>.\<HPS>|fpga_interfaces|<interface><space>.<BFM>.<API function>
Where:
• <DUT> is the instance name of the design under test that you instantiated in your test bench . The
design under test is the HPS component.
• <HPS> is the HPS component instance name that you use in your Qsys system.
• <interface> is the instance name of a specific FPGA-to-HPS or HPS-to-FPGA interface. This name can
be found in the fpga_interfaces.sv file located in <project directory>/<Qsys design name>/synthesis/
submodules.
• <space>—You must insert one space character after the interface instance name.
• <BFM> is the BFM instance name. To identify the BFM instance name, in <ACDS install>/ip/
altera/hps/postfitter_simulation, find the SystemVerilog file corresponding to the interface type that
you are using. This SystemVerilog file contains the BFM instance name.
For example, a path for the Lightweight HPS-to-FPGA master interface hierarchy could be formed as
follows:
top.dut.\my_hps_component|fpga_interface|hps2fpga_light_weight .h2f_lw_axi_master
Notice the space after
because the instance name
simulation model generated by the Quartus Prime software.

Clock and Reset Interfaces

Clock Interface
Qsys generates the BFM clock for each clock input interface from the FPGA component. For the FPGA-to-
HPS PLL reference clocks, specify the BFM reference clock frequency in the Reference clock frequency
field in the HPS Clocks page when instantiating the HPS component in Qsys.
Table 29-12: HPS Clock Input Interface Simulation Model
The Altera clock source BFM application programming interface (API) applies to all the BFMs listed in
this table. Your Verilog interfaces use the same API.
f2h_periph_ref_clock
f2h_sdram_ref_clock
Qsys generates the clock source BFM for each clock output interface from the HPS component. For
HPS-to-FPGA user clocks, specify the BFM clock rate in the User clock frequency field in the HPS
Clocks page when instantiating the HPS component in Qsys.
The HPS-to-FPGA TPIU generates a clock output to the FPGA, named
the clock source BFM also represents this clock output's behavior. Also, the HPS-to-FPGA debug APB
interface generates a clock output to the FPGA, named
Simulating the HPS Component
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hps2fpga_light_weight
hps2fpga_light_weight
Interface Name
BFM API Hierarchy Format
. Omitting this space would cause simulation failure
, including the space, is the name used in the post-fit
BFM Instance Name
f2h_periph_ref_clock_inst
f2h_sdram_ref_clock_inst
h2f_tpiu_clock
h2f_debug_apb_clock
29-9
. In simulation,
.
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