Fpga-To-Hps Sdram Interface - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Both HPS-to-FPGA interfaces are AXI-3 compliant. The HPS-side AXI bridges manage clock crossing,
buffering, and data width conversion where necessary.
Other interface standards in the FPGA fabric, such as connecting to Avalon-MM interfaces, can be
supported through the use of soft logic adaptors. The Qsys system integration tool automatically generates
adaptor logic to connect AXI to Avalon-MM interfaces.
Each AXI bridge accepts a clock input from the FPGA fabric and performs clock domain crossing
internally. The exposed AXI interface operates on the same clock domain as the clock supplied by the
FPGA fabric.
Related Information
• Clocks
Features of the HPS-FPGA Bridges
•
For more information, refer to the HPS FPGA AXI Bridges Component chapter.

FPGA-to-HPS SDRAM Interface

The FPGA-to-HPS SDRAM interface is a direct connection between the FPGA fabric and the HPS
SDRAM controller. This interface is highly configurable, allowing a mix between number of ports and port
width. The interface supports both AXI-3 and Avalon-MM protocols.
Table 28-3: FPGA-to-HPS SDRAM Interfaces and Clocks
Interface Name
f2h_sdram0_data
f2h_sdram1_data
f2h_sdram2_data
f2h_sdram3_data
f2h_sdram4_data
f2h_sdram5_data
The FPGA-to-HPS SDRAM interface is a configurable interface to the multi-port SDRAM controller.
The total data width of all interfaces is limited to a maximum of 256 bits in the read direction and 256 bits
in the write direction. The interface is implemented as four 64-bit read ports and four 64-bit write ports.
As a result, the minimum data width used by the interface is 64 bits, regardless of the number or type of
interfaces.
HPS Component Interfaces
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on page 28-4
SDRAM AXI or Avalon-MM port 0
SDRAM AXI or Avalon-MM port 1
SDRAM AXI or Avalon-MM port 2
SDRAM AXI or Avalon-MM port 3
SDRAM AXI or Avalon-MM port 4
SDRAM AXI or Avalon-MM port 5
on page 8-1
Description
FPGA-to-HPS SDRAM Interface
Associated Clock Interface
f2h_sdram0_clock
f2h_sdram1_clock
f2h_sdram2_clock
f2h_sdram3_clock
f2h_sdram4_clock
f2h_sdram5_clock
Altera Corporation
28-3