Simulation Flows - Altera cyclone V Technical Reference

29-2

Simulation Flows

Figure 29-1: HPS BFM Block Diagram
The HPS BFMs use standard function calls from the Altera BFM application programming interface
(API), as detailed in the remainder of this chapter.
HPS simulation supports only Verilog HDL or SystemVerilog simulation environments. Users with VHDL
Custom IP can run BFM simulations so long as a mixed-language simulation license is available on their
chosen simulator.
Related Information
Simulation Flows
•
• Instantiating the HPS Component
Avalon Verification IP Suite User Guide
•
Mentor Verification IP Altera Edition User Guide
•
Simulation Flows
Altera provides a functional register transfer level (RTL) simulation and a post–fitter gate–level simulation
flow. Both simulation flows involve the following major steps, which is defined in the following sections:
1. Setting up the HPS component for simulation.
2. Generating the HPS simulation model in Qsys.
3. Running the simulation.
Related Information
Simulating Altera Designs
For general information about simulation, refer to the Simulating Altera Designs chapter in volume 3 of the
Quartus Prime Handbook.
Altera Corporation
Hard Processor System
AXI HPS Master BFM
AXI HPS Slave BFM
SDRAM Memory Model
Interrupt Sink BFM
Conduit BFM
on page 29-2
on page 27-1
AXI Protocol Master
IP Components
AXI Protocol Slave
IP Components
Qsys
Interconnect
Avalon-MM
IP Components
2016.10.28
Simulating the HPS Component
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