Dma Controller Interface - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Figure 19-13: Single SPI Serial Master Microwire Serial Transfer (MDD=0)
sclk_out
ssi_oe_n
Figure 19-14: Single SPI Slave Microwire Serial Transfer (MDD=1)
sclk_out
ss_in_0
ssi_oe_n

DMA Controller Interface

The SPI controller supports DMA signaling to indicate when the receive FIFO buffer has data ready to be
read or when the transmit FIFO buffer needs data. It requires two DMA channels, one for transmit data
and one for receive data. The SPI controller can issue single or burst DMA transfers and accepts burst
acknowledges from the DMA. System software can trigger the DMA burst mode by programming an
appropriate value into the threshold registers. The typical setting of the threshold register value is half full.
To enable the DMA Controller interface on the SPI controller, you must write the DMA Control Register
( ). Writing a 1 into the
DMACR
interface. Writing a 1 into the
interface. †
Slave Interface
The host processor accesses data, control, and status information about the SPI controller through the
slave interface. The SPI supports a data bus width of 32 bits.
SPI Controller
Send Feedback
Control Word
txd
MSB
rxd
txd
Control Word
MSB
rxd
bit field of
TDMAE
RDMAE
LSB
MSB
0 MSB
LSB
register enables the SPI transmit handshaking
DMACR
bit field of the register enables the SPI receive handshaking
DMACR
DMA Controller Interface
4 - 16 Bits
LSB
Data Word
LSB
19-21
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