Altera cyclone V Technical Reference page 1140

cv_5v4
2016.10.28
indwr Fields
Bit
7:6
indcnt
5
inddone
4
rdqueued
3
sramfull
2
rdstat
1
cancel
0
start
Quad SPI Flash Controller
Send Feedback
Name
This field contains the count of indirect operations
which have been completed. This is used in conjunc‐
tion with the indirect completion status field (bit 5).
This field is set to 1 when an indirect operation has
completed. Write a 1 to this field to clear it.
Value
0x1
0x0
Two indirect write operations have been queued
Value
0x1
0x0
Indirect write operation in progress (status)
Value
0x1
0x0
Writing a 1 to this bit will cancel all ongoing indirect
write operations.
Value
0x1
0x0
Writing a 1 to this bit will trigger an indirect write
operation. The assumption is that the indirect start
address and the indirect number of bytes register is
setup before triggering the indirect write operation.
Value
0x1
0x0
Description
Description
Indirect operation completed
No Action
Description
Two Indirect write operation
No Action
Description
Indirect write operation
No Action
Description
Cancel Indirect write operation
No Action
Description
Trigger indirect write operation
No Action
15-51
indwr
Access Reset
RO 0x0
RW 0x0
RO 0x0
RO 0x0
RO 0x0
RW 0x0
RW 0x0
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