Altera cyclone V Technical Reference page 1130

cv_5v4
2016.10.28
Bit
4
protwrattempt
3
indrdreject
2
indopdone
1
underflowdet
irqmask
If disabled, the interrupt for the corresponding interrupt status register bit is disabled. If enabled, the
interrupt for the corresponding interrupt status register bit is enabled.
Module Instance
qspiregs
Offset:
0x44
Access:
RW
Quad SPI Flash Controller
Send Feedback
Name
Write to protected area was attempted and rejected.
Value
0x1
0x0
Indirect operation was requested but could not be
accepted. Two indirect operations already in storage.
Value
0x1
0x0
Controller has completed last triggered indirect
operation
Value
0x1
0x0
An underflow is detected when an attempt to transfer
data is made when the transmit FIFO is empty. This
may occur when the AHB write data is being supplied
too slowly to keep up with the requested write
operation. This bit is reset only by a system reset and
cleared only when the register is read.
Value
0x1
0x0
0xFF705000
Description
Description
Write Attempt to protected area
No Write Attempt
Description
Indirect Operation Requested
No Indirect Operation
Description
Completed Indirect Operation
No Indirect Operation
Description
Underflow
No Underflow
Base Address
0xFF705044
15-41
irqmask
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Register Address
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