Altera cyclone V Technical Reference page 1037

cv_5v4
2016.10.28
31 30
15 14
clkdiv Fields
Bit
7:0
clk_divider0
clksrc
Selects among available clock dividers. The sdmmc_cclk_out is always from clock divider 0.
Module Instance
sdmmc
Offset:
0xC
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
SD/MMC Controller
Send Feedback
29 28 27 26
13 12 11 10
Reserved
Name
Clock divider-0 value. Clock division is 2*n. For
example, value of 0 means divide by 2*0 = 0 (no
division, bypass), value of 1 means divide by 2*1 = 2,
value of ff means divide by 2*255 = 510, and so on.
0xFF704000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
21 20 19 18
5 4 3 2
clk_divider0
RW 0x0
Access
Register Address
0xFF70400C
21 20 19 18
5 4 3 2
14-91
clksrc
17 16
1 0
Reset
RW 0x0
17 16
1 0
clk_source
RW 0x0
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