Altera cyclone V Technical Reference page 1063

cv_5v4
2016.10.28
Bit
4
txdr
3
dto
2
cmd
1
re
0
cd
status
Reports various operting status conditions.
SD/MMC Controller
Send Feedback
Name
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Description
Description
Transmit FIFO data request (TXDR)
Clears Transmit FIFO data request (TXDR)
Description
Data transfer over (DTO)
Clears Data transfer over (DTO)
Description
Command done (CD)
Clears Command done (CD)
Description
Response error (RE)
Clears Response error (RE)
Description
Card detect (CD)
Clears Card detect (CD)
14-117
status
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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