Altera cyclone V Technical Reference page 1123

15-34
indaddrtrig
indaddrtrig
Module Instance
qspiregs
Offset:
0x1C
Access:
RW
31 30
15 14
indaddrtrig Fields
Bit
31:0
addr
dmaper
Module Instance
qspiregs
Offset:
0x20
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
29 28 27 26
13 12 11 10
Name
This is the base address that will be used by the AHB
controller. When the incoming AHB read access
address matches a range of addresses from this trigger
address to the trigger address + 15, then the AHB
request will be completed by fetching data from the
Indirect Controllers SRAM.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
0xFF705000
Bit Fields
25 24 23 22
addr
RW 0x0
9 8 7 6
addr
RW 0x0
Description
Base Address
0xFF705000
Register Address
0xFF70501C
21 20 19 18
5 4 3 2
Access
Register Address
0xFF705020
Quad SPI Flash Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
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