Altera cyclone V Technical Reference page 1142

cv_5v4
2016.10.28
31 30
15 14
indwrstaddr Fields
Bit
31:0
addr
indwrcnt
Module Instance
qspiregs
Offset:
0x7C
Access:
RW
31 30
15 14
indwrcnt Fields
Bit
31:0
value
Quad SPI Flash Controller
Send Feedback
29 28 27 26
13 12 11 10
Name
This is the start address from which the indirect
access will commence its write operation.
0xFF705000
29 28 27 26
13 12 11 10
Name
This is the number of bytes that the indirect access
will consume. This can be bigger than the configured
size of SRAM.
Bit Fields
25 24 23 22
addr
RW 0x0
9 8 7 6
addr
RW 0x0
Description
Base Address
Bit Fields
25 24 23 22
value
RW 0x0
9 8 7 6
value
RW 0x0
Description
indwrcnt
21 20 19 18
5 4 3 2
Access
Register Address
0xFF70507C
21 20 19 18
5 4 3 2
Access
15-53
17 16
1 0
Reset
RW 0x0
17 16
1 0
Reset
RW 0x0
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