Altera cyclone V Technical Reference page 1139

15-50
indwr
Offset:
0x6C
Access:
RW
31 30
15 14
indrdcnt Fields
Bit
31:0
value
indwr
Module Instance
qspiregs
Offset:
0x70
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
29 28 27 26
13 12 11 10
Name
This is the number of bytes that the indirect access
will consume. This can be bigger than the configured
size of SRAM.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
value
RW 0x0
9 8 7 6
value
RW 0x0
Description
Base Address
0xFF705000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
indcnt
RO 0x0
21 20 19 18
5 4 3 2
Register Address
0xFF705070
21 20 19 18
5 4 3 2
inddo rdque sramf rdsta
ne ued ull t
RW RO RO RO
0x0 0x0 0x0 0x0
Quad SPI Flash Controller
cv_5v4
2016.10.28
17 16
1 0
Access Reset
RW 0x0
17 16
1 0
cance start
l
RW 0x0
RW
0x0
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