Altera cyclone V Technical Reference page 1113

Hard processor system

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enterxipnextrd

Altera Corporation

If XIP is enabled, then setting to disabled will cause

the controller to exit XIP mode on the next READ

instruction. If XIP is disabled, then setting to enabled

will inform the controller that the device is ready to

enter XIP on the next READ instruction. The

controller will therefore send the appropriate

command sequence, including mode bits to cause the

device to enter XIP mode. Use this register after the

controller has ensured the FLASH device has been

configured to be ready to enter XIP mode. Note : To

exit XIP mode, this bit should be set to 0. This will

take effect in the attached device only AFTER the

next READ instruction is executed. Software should

therefore ensure that at least one READ instruction is

requested after resetting this bit before it can be sure

XIP mode in the device is exited.

(Direct Access Mode Only) When enabled, the

incoming AHB address will be adapted and sent to

the FLASH device as (address + N), where N is the

value stored in the remap address register.

Allows DMA handshaking mode. When enabled the

QSPI will trigger DMA transfer requests via the DMA

peripheral interface.

Enter XIP Mode on next READ instruction

Exit XIP Mode on next READ instruction

Enable AHB Re-mapping

Disable AHB Re-mapping

Enable DMA Mode

Disable DMA Mode

Quad SPI Flash Controller

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