Altera cyclone V Technical Reference page 1084

14-138
idinten
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
idinten Fields
Bit
9
ai
8
ni
5
ces
4
du
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This bit enables the following bits: IDINTEN[2] -
Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt
IDINTEN[5] - Card Error Summary Interrupt
Value
0x1
0x0
Enable and Disable Normal Interrupt Summary
Value
0x1
0x0
Enable and disable Card Error Interrupt Summary
Value
0x1
0x0
When set along with Abnormal Interrupt Summary
Enable, the DU interrupt is enabled.
Value
0x1
0x0
Bit Fields
25 24 23 22
Reserved
9 8 7 6
ai ni Reserved
RW RW
0x0 0x0
Description
Description
Abnormal Interrupt Summary is enabled
Abnormal Interrupt Summary is disabled
Description
Normal Interrupt Summary is enabled
Normal Interrupt Summary is disabled
Description
Card Error Summary Interrupt is enabled
Card Error Summary Interrupt is disabled
Description
Descriptor Unavailable Interrupt is enabled
Descriptor Unavailable Interrupt is disabled
21 20 19 18
5 4 3 2
ces du Reser fbe
ved
RW RW RW
0x0 0x0 0x0
Access
cv_5v4
2016.10.28
17 16
1 0
ri ti
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
SD/MMC Controller
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