Altera cyclone V Technical Reference page 1126

cv_5v4
2016.10.28
Offset:
0x2C
Access:
RO
31 30
15 14
sramfill Fields
Bit
31:16
indwrpart
15:0
indrdpart
txthresh
Module Instance
qspiregs
Offset:
0x30
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Quad SPI Flash Controller
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29 28 27 26
13 12 11 10
Name
SRAM fill level (Indirect Write Partition) in units of
SRAM words (4 bytes)
SRAM fill level (Indirect Read Parition) in units of
SRAM words (4 bytes)
0xFF705000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
indwrpart
RO 0x0
9 8 7 6
indrdpart
RO 0x0
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
txthresh
21 20 19 18
5 4 3 2
Access
Register Address
0xFF705030
21 20 19 18
5 4 3 2
RW 0x1
15-37
17 16
1 0
Reset
RO 0x0
RO 0x0
17 16
1 0
level
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