Altera cyclone V Technical Reference page 1017

cv_5v4
2016.10.28
Recommended Usage Guidelines for Card Read Threshold
1. The
cardthrctl
2. The
cardthrctl
3. The
cardrdthreshold
single or multiblock transfer. A
the read transfer ensures that the card clock does not stop in the middle of a block of data.
4. If the round trip delay is greater than half of the card clock period, card read threshold must be enabled
and the card threshold must be set as per guideline 3 to guarantee that the card clock does not stop in
the middle of a block of data.
5. If the
cardrdthreshold
the receive FIFO buffer never overflows during the read transfer. Overflow can cause the card clock
from the controller to stop. The controller is not able to guarantee that the card clock does not stop
during a read transfer.
Note: If the
dw_dma_multiple_transaction_size
clock might stop indefinitely, with no interrupts generated by the controller.
Card Read Threshold Programming Sequence
Most cards, such as SDHC or SDXC, support block sizes that are either specified in the card or are fixed to
512 bytes. For SDIO, MMC, and standard capacity SD cards that support partial block read
(READ_BL_PARTIAL set to 1 in the CSD register of the card device), the block size is variable and can be
chosen by the application.
To use the card read threshold feature effectively and to guarantee that the card clock does not stop
because of a FIFO Full condition in the middle of a block of data being read from the card, follow these
†
steps:
1. Choose a block size that is a multiple of four bytes.
2. Enable card read threshold feature. The card read threshold can be enabled only if the block size for the
given transfer is less than or equal to the total depth of the FIFO buffer:
(block size / 4) ≤ 1024
3. Choose the card read threshold value:
• If (block size / 4) ≥ 512, choose
•
cardrdthreshold
• If (block size / 4) < 512, choose
•
cardrdthreshold
4. Set the
dw_dma_multiple_transaction_size
that make up a DMA transaction. For example, size = 1 means 4 bytes are moved. The possible values
for the size are 1, 4, 8, 16, 32, 64, 128, and 256 transfers. Select the size so that the value (block size / 4)
is evenly divided by the size.
5. Set the
rx_wmark
For example, if your block size is 512 bytes, legal values of
are listed in the following table.
rx_wmark
SD/MMC Controller
Send Feedback
register must be set before setting the
register must not be set while a data transfer command is in progress.
field of the
cardrdthreshold
†
field is set to less than the block size of the transfer, the host must ensure that
†
field of the
cardrdthreshold
†
†
≤ (block size / 4) in bytes
= (block size / 4) in bytes
†
field in the
fifoth
Recommended Usage Guidelines for Card Read Threshold
register for a data read command.
cmd
register must be set to at the least the block size of a
cardthrctl
field setting greater than or equal to the block size of
register, and the
cardthrctl
fields of the
fifoth
†
†
such that:
cardrdthreshold
†
such that:
cardrdthreshold
†
field in the
fifoth
†
register to the size – 1.
dw_dma_multiple_transaction_size
†
and
rx_wmark
register are set incorrectly, the card
†
†
†
†
register to the number of transfers
Altera Corporation
14-71
†
†
and