Altera cyclone V Technical Reference page 1078

14-132
bmod
31 30
15 14
Reserved
bmod Fields
Bit
10:8
pbl
7
de
6:2
dsl
Altera Corporation
29 28 27 26
13 12 11 10
Name
These bits indicate the maximum number of beats to
be performed in one IDMAC transaction. The
IDMAC will always attempt to burst as specified in
PBL each time it starts a Burst transfer on the host
bus. This value is the mirror of MSIZE of FIFOTH
register. In order to change this value, write the
required value to FIFOTH register. This is an encode
value as follows.
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Enables and Disables Internal DMA.
0x1
0x0
Specifies the number of HWord/Word/Dword
(depending on 16/32/64-bit bus) to skip between two
unchained descriptors.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
pbl de
RO 0x0 RW
0x0
Description
Value
Transfer 1
Transfer 4
Transfer 8
Transfer 16
Transfer 32
Transfer 64
Transfer 128
Transfer 256
Value Description
IDMAC Enable
IDMAC Disable
21 20 19
5 4 3
dsl
RW 0x0
Description
cv_5v4
2016.10.28
18 17 16
2 1 0
fb swr
RW RW 0x0
0x0
Access Reset
RO 0x0
RW 0x0
RW 0x0
SD/MMC Controller
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