Altera cyclone V Technical Reference page 1045

cv_5v4
2016.10.28
Bit
8
rto
7
dcrc
6
rcrc
5
rxdr
4
txdr
3
dto
SD/MMC Controller
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Name
Bits used to mask unwanted interrupts. Value of 0
masks interrupts, value of 1 enables interrupt.
Value
0x0
0x1
Bits used to mask unwanted interrupts. Value of 0
masks interrupts, value of 1 enables interrupt.
Value
0x0
0x1
Bits used to mask unwanted interrupts. Value of 0
masks interrupts, value of 1 enables interrupt.
Value
0x0
0x1
Bits used to mask unwanted interrupts. Value of 0
masks interrupts, value of 1 enables interrupt.
Value
0x0
0x1
Bits used to mask unwanted interrupts. Value of 0
masks interrupts, value of 1 enables interrupt.
Value
0x0
0x1
Bits used to mask unwanted interrupts. Value of 0
masks interrupts, value of 1 enables interrupt.
Value
0x0
0x1
Description
Description
Response timeout Mask
Response timeout No Mask
Description
Data CRC error Mask
Data CRC error No Mask
Description
Response CRC error Mask
Response CRC error No Mask
Description
Receive FIFO data request Mask
Receive FIFO data request No Mask
Description
Transmit FIFO data request Mask
Transmit FIFO data request No Mask
Description
Data transfer over Mask
Data transfer over No Mask
14-99
intmask
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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