Altera cyclone V Technical Reference page 1112

Hard processor system
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cv_5v4
2016.10.28
Bit
22:19
bauddiv
18
enterxipimm
Quad SPI Flash Controller
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Name
SPI baud rate = ref_clk / (2 * baud_rate_divisor)
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
If XIP is enabled, then setting to disabled will cause
the controller to exit XIP mode on the next READ
instruction. If XIP is disabled, then setting enable will
operate the device in XIP mode immediately. Use this
register when the external device wakes up in XIP
mode (as per the contents of its non- volatile configu‐
ration register)​. The controller will assume the next
READ instruction will be passed to the device as an
XIP instruction, and therefore will not require the
READ opcode to be transferred. Note: To exit XIP
mode, this bit should be set to 0. This will take effect
in the attached device only after the next READ
instruction is executed. Software therefore should
ensure that at least one READ instruction is requested
after resetting this bit in order to be sure that XIP
mode is exited.
Value
0x1
0x0
Description
Description
Baud Rate Div/2
Baud Rate Div/4
Baud Rate Div/6
Baud Rate Div/8
Baud Rate Div/10
Baud Rate Div/12
Baud Rate Div/14
Baud Rate Div/16
Baud Rate Div/18
Baud Rate Div/20
Baud Rate Div/22
Baud Rate Div/24
Baud Rate Div/26
Baud Rate Div/28
Baud Rate Div/30
Baud Rate Div/32
Description
Enter XIP Mode immediately
Exit XIP Mode on next READ instruction
15-23
cfg
Access
Reset
RW
0xF
RW
0x0
Altera Corporation

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