Altera cyclone V Technical Reference page 1128

cv_5v4
2016.10.28
Offset:
0x40
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
irqstat Fields
Bit
12
indsramfull
11
rxfull
10
rxthreshcmp
Quad SPI Flash Controller
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
indsr rxful rxthr
amful l eshcm
l p
RW
RW 0x0 RW
0x0 0x0
Name
Indirect Read Partition of SRAM is full and unable to
immediately complete indirect operation
Value
0x1
0x0
Indicates that the receive FIFO is full or not. Only
relevant in SPI legacy mode.
Value
0x0
0x1
Indicates the number of entries in the receive FIFO
with respect to the threshold specified in the
RXTHRESH register. Only relevant in SPI legacy
mode.
Value
0x0
0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
txful txthr rxove indxf
l eshcm r rlvl
p
RW RW RW
0x0 RW 0x0 0x0
0x1
Description
Description
SRAM is full
SRAM is not full
Description
Receive FIFO Not Full
Receive FIFO Full
Description
FIFO has <= RXTHRESH entries
FIFO has > RXTHRESH entries
21 20 19 18
5 4 3 2
illeg protw indrd indop
alacc ratte rejec done
mpt t
RW RW
0x0 RW RW 0x0
0x0 0x0
Access
15-39
irqstat
17 16
1 0
under Reserved
flowd
et
RW
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
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