Altera cyclone V Technical Reference page 1129

Hard processor system

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Indicates that the transmit FIFO is full or not. Only

relevant in SPI legacy mode.

Indicates the number of entries in the transmit FIFO

with respect to the threshold specified in the

TXTHRESH register. Only relevant in SPI legacy

This should only occur in Legacy SPI mode. Set if an

attempt is made to push the RX FIFO when it is full.

This bit is reset only by a system reset and cleared

only when this register is read. If a new push to the

RX FIFO occurs coincident with a register read this

flag will remain set. 0 : no overflow has been detected.

1 : an overflow has occurred.

Indirect Transfer Watermark Level Reached

Illegal AHB access has been detected. AHB wrapping

bursts and the use of SPLIT/RETRY accesses will

cause this error interrupt to trigger.

Transmit FIFO Not Full

Transmit FIFO Full

FIFO has > TXTHRESH entries

FIFO has <= TXTHRESH entries

Receive Overflow

No Receive Overflow

Water level reached

No water level reached

Illegal AHB attempt

No Illegal AHB attempt

Quad SPI Flash Controller

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