Altera cyclone V Technical Reference page 1082

14-136
idsts
Bit
9
ais
8
nis
5
ces
Altera Corporation
Name
Logical OR of the following: IDSTS[2] - Fatal Bus
Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] -
Card Error Summary Interrupt Only unmasked bits
affect this bit. This is a sticky bit and must be cleared
each time a corresponding bit that causes AIS to be
set is cleared.
Value
0x1
0x0
Logical OR of the following: IDSTS[0] - Transmit
Interrupt IDSTS[1] - Receive Interrupt Only
unmasked bits affect this bit. This is a sticky bit and
must be cleared each time a corresponding bit that
causes NIS to be set is cleared.
Value
0x1
0x0
Indicates the status of the transaction to/from the
card; also present in RINTSTS. Indicates the logical
OR of the following bits: EBE - End Bit Error RTO -
Response Timeout/Boot Ack Timeout RCRC -
Response CRC SBE - Start Bit Error DRTO - Data
Read Timeout/BDS timeout DCRC - Data CRC for
Receive RE - Response Error
Value
0x1
0x0
Description
Description
Clears Abnormal Summary Interrupt Status
Bit
No Clear Abnormal Summary Interrupt
Status Bit
Description
Clears Normal Interrupt Summary Status Bit
No Clear Normal Interrupt Summary Status
Bit
Description
Clears Card Error Summary Interrupt Status
Bit
No Clear Card Error Summary Interrupt
Status Bit
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
SD/MMC Controller
Send Feedback