Altera cyclone V Technical Reference page 1034

14-88
ctrl
Bit
9
send_ccsd
8
abort_read_data
7
send_irq_response
Altera Corporation
Name
When set, SD/MMC sends CCSD to CE-ATA device.
Software sets this bit only if current command is
expecting CCS (that is, RW_BLK) and interrupts are
enabled in CE-ATA device. Once the CCSD pattern is
sent to device, SD/MMC automatically clears send_
ccsd bit. It also sets Command Done (CD) bit in
RINTSTS register and generates interrupt to host if
Command Done interrupt is not masked. NOTE:
Once send_ccsd bit is set, it takes two card clock
cycles to drive the CCSD on the CMD line. Due to
this, during the boundary conditions it may happen
that CCSD is sent to the CE-ATA device, even if the
device signalled CCS.
Value
0x0
0x1
After suspend command is issued during read-
transfer, software polls card to find when suspend
happened. Once suspend occurs software sets bit to
reset data state-machine, which is waiting for next
block of data. Bit automatically clears once data
statemachine resets to idle. Used in SDIO card
suspend sequence.
0x0
0x1
Bit automatically clears once response is sent. To wait
for MMC card interrupts, host issues CMD40, and
SD/MMC waits for interrupt response from MMC
card(s). In meantime, if host wants SD/MMC to exit
waiting for interrupt state, it can set this bit, at which
time SD/MMC command state-machine sends
CMD40 response on bus and returns to idle state.
Value
0x0
0x1
Description
Description
Clear bit if SD/MMC does not reset the bit
Send Command Completion Signal Disable
(CCSD) to CE-ATA device
Value Description
No change
Abort Read
Description
No change
Send auto IRQ response
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
SD/MMC Controller
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