Altera cyclone V Technical Reference page 1110

cv_5v4
2016.10.28
Register
indrdwater on page
15-48
indrdstaddr on page
15-49
indrdcnt on page 15-
49
indwr on page 15-50
indwrwater on page
15-52
indwrstaddr on page
15-52
indwrcnt on page 15-
53
flashcmd on page 15-
54
flashcmdaddr
15-57
flashcmdrddatalo
page 15-58
flashcmdrddataup
page 15-58
flashcmdwrdatalo
page 15-59
flashcmdwrdataup
page 15-60
moduleid on page 15-
60
cfg
Module Instance
qspiregs
Offset:
0x0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Quad SPI Flash Controller
Send Feedback
Offset Width Acces
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
0x90
on page 0x94
on 0xA0
on 0xA4
on 0xA8
on 0xAC
0xFC
0xFF705000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Reset Value
s
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0xFFFFFFFF
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RO 0x1001
Base Address
cfg
Description
Indirect Read Transfer Watermark
Register
Indirect Read Transfer Start
Address Register
Indirect Read Transfer Number
Bytes Register
Indirect Write Transfer Register
Indirect Write Transfer
Watermark Register
Indirect Write Transfer Start
Address Register
Indirect Write Transfer Count
Register
Flash Command Register
Flash Command Address
Registers
Flash Command Read Data
Register (Lower)
Flash Command Read Data
Register (Upper)
Flash Command Write Data
Register (Lower)
Flash Command Write Data
Register (Upper)
Module ID Register
Register Address
0xFF705000
Altera Corporation
15-21