Altera cyclone V Technical Reference page 1111

15-22
cfg
31 30
idle
RO 0x0
15 14
endma wp
RW 0x0 RW
0x0
cfg Fields
Bit
31
idle
Altera Corporation
29 28 27 26
Reserved
13 12 11 10
percslines
RW 0x0
Name
This is a STATUS read-only bit. Note this is a retimed
signal, so there will be some inherent delay on the
generation of this status signal.
0x1
0x0
Bit Fields
25 24 23 22
9 8 7 6
perse enleg endir
ldec acyip acc
RW RW RW
0x0 0x0 0x0
Description
Value Description
Idle Mode
Non-Idle Mode
21 20 19 18
bauddiv enter
xipim
RW 0xF
m
RW
0x0
5 4 3 2
Reserved selcl
kphas
e
RW
0x0
Access
Quad SPI Flash Controller
cv_5v4
2016.10.28
17 16
enter enahbrem
xipne ap
xtrd
RW 0x0
RW
0x0
1 0
selcl en
kpol
RW 0x0
RW
0x0
Reset
RO 0x0
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