Altera cyclone V Technical Reference page 1038

14-92
clkena
clksrc Fields
Bit
1:0
clk_source
clkena
Controls external SD/MMC Clock Enable.
Module Instance
sdmmc
Offset:
0x10
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
Selects among available clock dividers. The SD/MMC
module is configured with just one clock divider so
this register should always be set to choose clkdiv0.
0x0
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Description
Value
Clock divider 0
Base Address
0xFF704000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Register Address
0xFF704010
21 20 19
5 4 3
cv_5v4
2016.10.28
Access Reset
RW 0x0
18 17 16
cclk_
low_
power
RW 0x0
2 1 0
cclk_
enable
RW 0x0
SD/MMC Controller
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