Altera cyclone V Technical Reference page 1083

cv_5v4
2016.10.28
Bit
4
du
2
fbe
1
ri
0
ti
idinten
Various DMA Interrupt Enable Status
Module Instance
sdmmc
Offset:
0x90
Access:
RW
SD/MMC Controller
Send Feedback
Name
This status bit is set when the descriptor is unavailable
due to OWN bit = 0 (DES0[31] =0).
Value
0x1
0x0
Indicates that a Bus Error occurred (IDSTS[12:10]).
When setthe DMA disables all its bus accesses.
Value
0x1
0x0
Indicates the completion of data reception for a
descriptor
Value
0x1
0x0
Indicates that data transmission is finished for a
descriptor.
Value
0x1
0x0
0xFF704000
Description
Description
Clears Descriptor Unavailable Interrupt
Status Bit
No Clear of Descriptor Unavailable Interrupt
Status Bit
Description
Clears Fatal Bus Error Interrupt Status Bit
No Clear of Fatal Bus Error Interrupt Status
Bit
Description
Clears Receive Interrupt Status Bit
No Clear of Receive Interrupt Status Bit
Description
Clears Transmit Interrupt Status Bit
No Clear of Transmit Interrupt Status Bit
Base Address
idinten
Access
Register Address
0xFF704090
14-137
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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