Altera cyclone V Technical Reference page 1058

14-112
mintsts
Bit
11
fifoovunerr
10
dshto
9
datardto
8
respto
7
datacrcerr
6
respcrcerr
Altera Corporation
Name
Interrupt enabled only if corresponding bit in
interrupt mask register is set.
Value
0x0
0x1
Interrupt enabled only if corresponding bit in
interrupt mask register is set.
Value
0x0
0x1
Interrupt enabled only if corresponding bit in
interrupt mask register is set.
Value
0x0
0x1
Interrupt enabled only if corresponding bit in
interrupt mask register is set.
Value
0x0
0x1
Interrupt enabled only if corresponding bit in
interrupt mask register is set.
Value
0x0
0x1
Interrupt enabled only if corresponding bit in
interrupt mask register is set.
Value
0x0
0x1
Description
Description
FIFO underrun/overrun error Mask
FIFO underrun/overrun error No Mask
Description
Data starvation by host timeout Mask
Data starvation by host timeout No Mask
Description
Data read timeout Mask
Data read timeout No Mask
Description
Response timeout Mask
Response timeout No Mask
Description
Data CRC error Mask
Data CRC error No Mask
Description
Response CRC error Mask
Response CRC error No Mask
cv_5v4
2016.10.28
Access Reset
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
SD/MMC Controller
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