Altera cyclone V Technical Reference page 1141

15-52
indwrwater
indwrwater
Module Instance
qspiregs
Offset:
0x74
Access:
RW
31 30
15 14
indwrwater Fields
Bit
31:0
level
indwrstaddr
Module Instance
qspiregs
Offset:
0x78
Access:
RW
Altera Corporation
29 28 27 26
13 12 11 10
Name
This represents the maximum fill level of the SRAM
before a DMA peripheral access is permitted. When
the SRAM fill level falls below the watermark, an
interrupt is also generated. This field can be disabled
by writing a value of all ones. The units of this register
are bytes.
Base Address
0xFF705000
Bit Fields
25 24 23 22
level
RW 0xFFFFFFFF
9 8 7 6
level
RW 0xFFFFFFFF
Description
Base Address
0xFF705000
Register Address
0xFF705074
21 20 19 18
5 4 3 2
Access
Register Address
0xFF705078
Quad SPI Flash Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0xFFFFF
FFF
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