Altera cyclone V Technical Reference page 1115

15-26
devrd
Bit
7
endiracc
2
selclkphase
1
selclkpol
0
en
devrd
Module Instance
qspiregs
Altera Corporation
Name
If disabled, the Direct Access Controller becomes
inactive once the current transfer of the data word
(FF_W) is complete. When the Direct Access
Controller and Indirect Access Controller are both
disabled, all AHB requests are completed with an
error response.
Value
0x0
0x1
Selects whether the clock is in an active or inactive
phase outside the SPI word.
Value
0x0
0x1
Controls spiclk modes of operation.
Value
0x1
0x0
If this bit is clear, the QSPI finishes the current
transfer of the data word (FF_W) and stops sending.
When this bit is set to 1, the QSPI is enabled. If the
QSPI is enabled and qspi_n_mo_en=1, then the QSPI
is able to initiate transfers on the bus. If the QSPI is
enabled and qspi_n_mo_en = 0, all output enables are
inactive and all pins are set to input mode.
Value
0x0
0x1
0xFF705000
Description
Description
Disable Direct Access Ctrl
Enable Direct Access Ctrl
Description
SPI clock is quiescent low
Clock Inactive
Description
SPI clock is quiescent low
SPI clock is quiescent high
Description
Disable the QSPI
Enable the QSPI
Base Address
0xFF705004
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Register Address
Quad SPI Flash Controller
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cv_5v4