Altera cyclone V Technical Reference page 1094

cv_5v4
2016.10.28
AHB
The data slave interface is throttled as the read or write burst is carried out. The latency is designed to be as
small as possible and is kept to a minimum when the use of XIP read instructions are enabled.
FLASH erase operations, which may be required before a page write, are triggered by software using the
documented programming interface. They are not issued automatically.
Once a page program cycle has been started, the QSPI Flash Controller will automatically poll for the
write cycle to complete before allowing any further data slave interface accesses to complete. This is
achieved by holding any subsequent AHB direct accesses in wait state.
Indirect Access Mode
In indirect access mode, flash data is temporarily buffered in the quad SPI controller's static RAM
(SRAM). Software controls and triggers indirect accesses through the register slave interface. The
controller transfers data through the data slave interface.
Indirect Read Operation
An indirect read operation reads data from the flash memory, places the data into the SRAM, and
transfers the data to an external master through the data slave interface. The indirect read operations are
controlled by the following registers:
• Indirect read transfer register (
• Indirect read transfer watermark register (
• Indirect read transfer start address register (
• Indirect read transfer number bytes register (
• Indirect address trigger register (
These registers need to be configured prior to issuing indirect read operations. The start address needs to
be defined in the
register. Writing 1 to the start indirect read bit (
indircnt
read operation from the flash memory to populate the SRAM with the returned data.
To read data from the flash device into the SRAM, an external master issues 32-bit read transactions to the
data slave interface. The address of the read access must be in the indirect address range. You can
configure the indirect address through the
reads until the last word of an indirect transfer. On the final read, the external master may issue a 32-bit,
16-bit or 8-bit read to complete the transfer. If there are less than four bytes of data to read on the last
transfer, the external master can still issue a 32-bit read and the quad SPI controller will pad the upper bits
of the response data with zeros.
Assuming the requested data is present in the SRAM at the time the data slave read is received by the quad
SPI controller, the data is fetched from SRAM and the response to the read burst is achieved with
minimum latency. If the requested data is not immediately present in the SRAM, the data slave interface
enters a wait state until the data has been read from flash memory into SRAM. Once the data has been
read from SRAM by the external master, the quad SPI controller frees up the associated resource in the
SRAM. If the SRAM is full, reads on the SPI interface are backpressured until space is available in the
SRAM. The quad SPI controller completes any current read burst, waits for SRAM to free up, and issues a
new read burst at the address where the previous burst was terminated.
The processor can also use the SRAM fill level in the SRAM fill register (
should be fetched from the SRAM.
Quad SPI Flash Controller
Send Feedback
)
indrd
indaddrtrig
register and the total number of bytes to be fetched is specified in the
indrdstaddr
)
indrdwater
)
indrdstaddr
)
indrdcnt
)
) of the
start
register. The external master can issue 32-bit
indaddrtrig
AHB
register triggers the indirect
indrd
) to control when data
sramfill
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