Altera cyclone V Technical Reference page 1116

cv_5v4
2016.10.28
Offset:
0x4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
Reserved
devrd Fields
Bit
28:24
dummyrdclks
20
enmodebits
Quad SPI Flash Controller
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
dummyrdclks
RW 0x0
13 12 11 10
addrwidth Reserved
RW 0x0
Name
Number of dummy clock cycles required by device for
read instruction.
If this bit is set, the mode bits as defined in the Mode
Bit Configuration register are sent following the
address bytes.
Value
0x0
0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
instwidth
RW 0x0
Description
Description
No Order
Mode Bits follow address bytes
devrd
21 20 19 18
enmod Reserved
ebits
RW
0x0
5 4 3 2
rdopcode
RW 0x3
Access
RW
RW
15-27
17 16
datawidth
RW 0x0
1 0
Reset
0x0
0x0
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