Altera cyclone V Technical Reference page 1060

14-114
rintsts
rintsts
Interrupt Status Before Masking.
Module Instance
sdmmc
Offset:
0x44
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
ebe acd
RW 0x0 RW
0x0
rintsts Fields
Bit
16
sdio_interrupt
15
ebe
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
sbe hle frun hto
RW RW RW RW
0x0 0x0 0x0 0x0
Name
Interrupt from SDIO card.
Value
0x1
0x0
Writes to bits clear status bit. Value of 1 clears status
bit, and value of 0 leaves bit intact. Bits are logged
regardless of interrupt mask status.
Value
0x0
0x1
Base Address
0xFF704000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
bds bar dcrc rcrc
RW RW RW RW
0x0 0x0 0x0 0x0
Description
Description
SDIO interrupt from card bit
No SDIO interrupt from card bi
Description
End-bit error (read)/write no CRC (EBE)
Clears End-bit error (read)/write no CRC
(EBE)
Register Address
0xFF704044
21 20 19 18
5 4 3 2
rxdr txdr dto cmd
RW RW RW RW
0x0 0x0 0x0 0x0
Access
cv_5v4
2016.10.28
17 16
sdio_
interrup
t
RW 0x0
1 0
re cd
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
SD/MMC Controller
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