Altera cyclone V Technical Reference page 1036

14-90
clkdiv
Module Instance
sdmmc
Offset:
0x4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
pwren Fields
Bit
0
power_enable
clkdiv
Divides Clock sdmmc_clk.
Module Instance
sdmmc
Offset:
0x8
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Power on/​off switch for one card; for example, bit[0]
controls the card. Once power is turned on, firmware
should wait for regulator/switch ramp-up time before
trying to initialize card.
0x0
0x1
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
0xFF704000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Value
Power Off
Power On
Base Address
0xFF704000
Register Address
0xFF704004
21 20 19 18
5 4 3
Description
Register Address
0xFF704008
cv_5v4
2016.10.28
17 16
2 1 0
power_
enable
RW 0x0
Access Reset
RW 0x0
SD/MMC Controller
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